1. Field of the Invention
The present invention relates to a method for polishing an organic film, such as a resist or the like, on a semiconductor substrate, by use of resin particles, and slurry for use in the polishing.
2. Description of the Related Art
As conventional techniques, there is a tape-like polishing agent prepared by applying thermosetting resin particles and a binder onto a film base material and then drying them (e.g., see page 3 of Jpn. Pat. Appln. KOKOKU Publication No. 2-51951), and there is known a micro-spherical polishing agent made of a melamine phenol polyimide resin, and a co-rubbing polishing method (e.g., see page 2 of Jpn. Pat. Appln. KOKAI Publication No. 2001-277105). In addition, there is a method for subjecting to CMP treatment a resist surface cured by an ion beam implantation or plasma etching (e.g., see page 1 and FIG. 4 of U.S. Pat. No. 6,235,636), and a chemical mechanical polishing of a resist which comprises pressing a polishing cloth against a wafer while supplying fuming nitric acid (e.g., see the abstract and FIG. 3 of Jpn. Pat. Appln. KOKAI Publication No. 11-87307).
Until now, a chemical mechanical polishing method (CMP method) has been used in which a slurry containing silica particles is used as a polishing material, in flattening a surface of a semiconductor wafer having an uneven substrate on which fine slots and the like are formed, and a resist film deposited on the uneven substrate surface including inner surface parts of the slots and the like.
Description will now be made of a manufacturing method of a capacitor by use of the CMP method utilizing silica particles.
First, FIGS. 6A to 6C are sectional views showing a capacitor manufacturing process (trench structure) according to a first conventional example. Here, a region on a silicon substrate 61 in which deep and narrow slots DT (deep trench) are formed is referred to as a cell array section 6a, and a region in which no slots DT are formed is referred to as a field section 6b. 
As shown in FIG. 6A, the slots DT are formed in the silicon substrate 61 by using, e.g., an RIE technique. An ASG film 62 is formed on inner surfaces of the slots DT, and a resist film 63 is formed to a predetermined thickness to completely fill the slots DT. Accordingly, a surface of the resist film 63 in the cell array section 6a is lower than that in the field section 6b with respect to a flat surface indicated by a broken line, whereby a step is formed on the surface of the resist film 63.
Afterward, the resist film 63 is etched back in order to leave the resist film at a predetermined height from the slots DT. However, the etching-back step is a uniform etching operation carried out by using the surface of the resist film 63 as a reference, and therefore, it is impossible to form a resist film having a uniform height from the bottoms of the slots DT. As shown in FIG. 6B, resist films 631 to 636 having a nonuniform thickness on which the step shape of the resist film surface is reflected are formed in the respective slots DT.
Subsequently, the resist films 631 to 636 left in the respective slots DT are used as masks to etch the ASG film 62 not covered with the resist films 631 to 636, and then, the resist films 631 to 636 are etched off. Accordingly, heights of the resist films 631 to 636 are patterned in the ASG film 62 formed in the slots DT, whereby ASG films (not shown) having a nonuniform height are formed in the respective slots DT.
Then, an unillustrated tetraethoxy silane film (TEOS film) is formed on the silicon substrate 61 including inner surface parts of the slots DT, and a heat treatment is carried out to inject an impurity As contained in the ASG film into the silicon substrate 61, whereby an As diffused region 66 is formed. Thus, the As diffused region 66, in which heights in the slots DT are nonuniform, is formed as a common electrode of capacitors in the silicon substrate 61.
Afterward, the TEOS film and the ASG film are removed to form a nitric oxide film (NO film) 67 on the substrate, which includes the inner surface parts of the slots DT, whereby a capacitor insulating film is formed. Further, polysilicon is deposited to fill the slots DT.
Subsequently, the polysilicon is flattened to be on the same plane as a surface of the NO film 67, and other electrodes 681 to 686 are formed in the slots DT. Accordingly, capacitors as shown in FIG. 6C are formed.
The height of the As diffused region 66, which is the common electrode of the capacitors, is not uniform, and opposing areas of the As diffused region 66 and the NO film 67, which is a capacitor insulating film, are not uniform. Consequently, uniformity of opposing areas of electrodes for each capacitor cannot be secured, whereby capacitors having nonuniform capacity values are formed.
In order to deal with the formation of such nonuniform capacitors, the slots DT may be formed deeper to secure a minimum capacity sufficient for a semiconductor device. However, the formation of the deeper trenches DT may impose a performance/control load on a device manufacturing process, consequently causing a problem of impossibility of manufacturing a device of expected performance.
FIGS. 7A to 7D are sectional views showing a capacitor manufacturing process (trench structure) according to a second conventional example.
As shown in FIG. 7A, the plurality of slots DT are formed in a silicon substrate 61.
An ASG film 62 is formed on inner wall surfaces of the respective slots DT, and a resist film 63 is also formed. Accordingly, a surface of the resist film 63 in a cell array section 6a is lower than that in a field section 6b with respect to a flat surface indicated by a broken line, and a step is formed on the surface of the resist film 63.
Then, a known CMP method is used to polish the resist film 63. However, because of hard silica particles, polishing is carried out to the ASG film 62 below the resist film 63. Consequently, an erosion 71 or a scratch 72 shown in FIG. 7B occurs. In addition, the formation of the slots DT in the substrate 61 causes clogging 73, where openings of the slots DT are clogged with silica particles.
Then, as shown in FIG. 7C, resist films 741 to 746 are etched back. However, clogging of the opening with silica particles prevents etching-back of the resist film 743. Consequently, the height of the resist film 743 is not uniform with those of resist films 771 to 775.
Subsequently, each of the resist films 771 to 775, and the resist film 743 are used as masks to etch the ASG film 62. Then, the resist films 771 to 775, and the resist film 743 are etched off. Accordingly, heights of the resist films 771 to 775 and the resist film 743 are patterned in the ASG film 62 formed in the slots DT, whereby ASG films (not shown) having a nonuniform height are formed in the slots DT.
Then, an unillustrated tetraethoxy silane film (TEOS film) is formed on the substrate, which includes inner surface parts of the slots DT, and a heat treatment is carried out to inject an impurity contained in the ASG film into the silicon substrate 61, whereby an As diffused region 75 is formed. Thus, the nonuniform As diffused region 75 is formed as a common electrode of capacitors in the silicon substrate 61.
Then, the TEOS film and the ASG film are removed to form a nitric oxide film (NO film) 67 on the substrate, which includes the inner surface parts of the slots DT, whereby a capacitor insulating film is formed. Further, polysilicon is deposited on the substrate 61 including the inner side of the slots DT. Then, the polysilicon is etched to be flattened on the surface of the NO film 67, thereby forming other electrodes 761 to 766. Accordingly, capacitors as shown in FIG. 7D are formed.
The height of the As diffused region 66 in the slots DT, which is the common electrode of the capacitors, is not uniform, and opposing areas of the As diffused region 66 and the NO film 67, which is a capacitor insulating film, are not uniform. Consequently, equal opposing areas of electrodes for capacitors cannot be secured, thus capacitors having nonuniform capacity values are formed. Therefore, the above-described problem occurs.
FIGS. 8A to 8C are sectional views showing a capacitor manufacturing process (stack structure) according to a third conventional example.
As shown in FIG. 8A, on a substrate 81, an insulating film 82 is formed flat to a predetermined thickness, and slots SN (storage node) are formed by using an RIE technique. A polysilicon film 83 is formed to be uniform in thickness on a surface of the insulating film 82, which includes inner surface parts of the slots SN, and a resist film 84 is formed to a predetermined thickness to fill the slots SN.
Then, silica particles are used to polish upper parts of the resist film 84 and the polysilicon film 83 by a CMP method, whereby resist masks 841 to 845 are formed. Consequently, an erosion 85 or a scratch 86 shown in FIG. 8B occurs. In addition, an opening of a slot SN is clogged with silica particles, which form a clogging 87.
Then, the resist masks 841 to 845 are etched off. However, because of the clogging 87 at the opening of the slot SN, the resist mask 843 is left unetched. Then, the insulating film 82 is etched to simultaneously remove the clogging 87. However, the resist mask 843 may still remains.
Subsequently, a nitric oxide film (NO film) 89 is formed on polysilicon electrodes 831 to 835 and the substrate 61 to form a capacitor insulating film 89. Then, a polysilicon electrode 88 is formed on the NO film 89 to form an opposite common electrode of capacitors.
Accordingly, because of the electrodes, opposing areas of which are nonuniform, the capacitors have nonuniform capacity values. In addition, the resist mask 843 is left unetched. Consequently, this section has lost its function as a capacitor.
Furthermore, in order to deal with the formation of such nonuniform capacity values, the slots SN may be formed higher to secure a minimum capacity sufficient for a semiconductor device. However, the formation of the higher slots SN may impose a performance/control load on a device manufacturing process, consequently causing a problem of impossibility of manufacturing a semiconductor device of expected performance.